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SP5748
2.4GHz Very Low Phase Noise PLL Datasheet
DS4875 ISSUE 2.3 November 2001
Features
* Complete 2.4 GHz Single Chip System (for faster device refer to SP5768) * Optimised for Low Phase Noise, with Comparison Frequencies up to 4 MHz * No RF Prescaler * Selectable Reference Division Ratio * Reference Frequency Output * Selectable Charge Pump Current * Integrated Loop Amplifier * Two Switching Ports * Low Power Replacement for SP5658 and SP5668 * Power Consumption 110mW with VCC = 5*5V and all Ports off * Downwards Software Compatible with SP5658 * ESD Protection 2kV min., MIL-STD-883B Method 3015 Cat.1 (Normal ESD handling procedures should be observed)
Ordering Information
SP5748/KG/MP1S (Tubes) SP5748/KG/MP1T (Tape and Reel) (14 lead minature plastic package) SP5748/KG/QP1S (Tubes) SP5748/KG/QP1T (Tape and Reel) (16 lead QSOP plastic Package)
and allows for coarse tuning in the up-converter application and fine tuning in the down-converter. Comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. A buffered reference frequency output is also available to drive a second SP5748. The device also contains 2 switching ports.
Absolute Maximum Ratings
Supply voltage, VCC RF differential input voltage RF input DC offset Port voltage Charge pump DC offset Varactor drive DC offset Crystal DC offset Buffered reference output Data, clock and enable DC offset Storage temperature Junction temperature MP14 thermal resistance Chip to ambient, JA Chip to case, JC -0*3V to +7V 2*5V -0*3 to VCC +0*3V -0*3 to VCC +0*3V -0*3 to VCC +0*3V -0*3 to VCC +0*3V -0*3 to VCC +0*3V -0*3 to VCC +0*3V -0*3 to VCC +0*3V -55C to +125C +150C 81C/W 27C/W
Applications
* TV, VCR and Cable Tuning Systems * Communications Systems
Description
The SP5748 is a single chip frequency synthesiser designed for tuning systems up to 2.4 GHz and is optimized for low phase noise with comparison frequencies up to 4 MHz. It is designed to be downwards software compatible with the SP5658. The RF programmable divider contains a front end dual-modulus 416/17 functioning over the full operating range
2 11
CRYSTAL CAP
RF INPUT
13-BIT COUNT
REFERENCE DIVIDER
3 1
12
416/17
4-BIT COUNT CHARGE PUMP
CRYSTAL PUMP DRIVE
14
17-BIT LATCH DATA CLOCK ENABLE
5 6 4
6-BIT LATCH
9
REF
DATA INTERFACE 3-BIT LATCH AND PORT/TEST MODE INTERFACE
7 8
PORT P1/OC PORT P0/OP
Figure 1 SP5748 Block Diagram (MP14 pinout)
SP5748
Datasheet
CHARGE PUMP CRYSTAL CAP CRYSTAL ENABLE DATA CLOCK PORT P1/OC
1 2 3 4 5 6 7
14 13 12
DRIVE VEE RF INPUT RFINPUT VCC REF PORTP0/OP
SP 5748
11 10 9 8
CHARGE PUMP CRYSTAL CAP CRYSTAL ENABLE DATA CLOCK PORT P1/OC PORT P0/OP
1 2 3 4 5 6 7 8
16 15 14
SP 5748
13 12 11 10 9
DRIVE VEE NC RF INPUT RF INPUT NC VCC REF
MP14
Figure 2 - Pin connections - top view
QP16
Electrical Characteristics
Test conditions (unless otherwise stated): Tamb = -40C to +80C, VCC = 4*5V to 5*5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Note: Pin numbers refer to MP14 package. Value Characteristic Supply current RF input Frequency range Input voltage Input impedance Data, clock and enable Input high voltage Input low voltage Input current Hysteresis Clock rate Bus timing Data set up Data hold Enable set up Enable hold Clock to enable Charge pump Output current Output leakage Drive output current Crystal frequency External reference Input frequency Drive level Buffered reference output Output amplitude Output impedance Pin 10 11,12 80 30 40 5,6,4 3 0 -10 0*8 6 5,6,4 300 600 300 600 300 1 1 14 2,3 2
3 10
Min.
Typ. 13
Max. 20
Units mA
Conditions
MHz -400 300 mVrms 150MHz to 2400MHz, see Figure 6 300 mVrms 80MHz to 150MHz, see Figure 6 See Figure 3 V CC 0*7 10 500 V V A Vp-p kHz ns ns ns ns ns A nA mA MHz MHz Vp-p Vp-p VPIN1 = 2V, See Table 1 VPIN1 = 2V, VCC = 15*0V, TAMB = 25C VPIN14 = 0*7V See Figure 5 for application Sinewave coupled via 10nF blocking capacitor Sinewave coupled via 10nF blocking capacitor AC coupled, see Note 1 2-20MHz cont...
All input conditions
0*5 2 2 0*2
20 20 0*5 0*35 250
9
2
Datasheet
Electrical Characteristics (continued)
Value Characteristic Comparison frequency Equivalent phase noise at phase detector RF division ratio Reference division ratio Output Ports P0 and P1 Sink current Leakage current Pin Min. Typ. -148 240 2 7,8 2 10 mA A 131071 320 Max. 4 Units Conditions
SP5748
MHz dBc/Hz At 10kHz SSB with 2MHz comparison from 4MHz crystal See Table 2 See Note 2 VPORT = 0*7V VPORT = VCC
NOTES 1. Reference output disabled by connecting to VCC. 2. Output ports high impedance on power-up, with data, clock and enable at logic `0'.
Functional description
The SP5748 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. The block diagram is shown in Figure 1 and packages and pin allocations in Figure 2. The SP5748 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word contains 26 bits, two of which are used for port selection, 17 to set the programmable divider ratio, 4 bits to select the reference division ratio (bits RD and R0-R2, see Table 2), two bits to set charge pump current, bits C0 and C1 (see Table 1) and the remaining bit to access test modes (bit T0, see Table 3)). The programming data format is shown in Figure 4. The clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 17-bit fully programmable counter, which is of MN+A architecture. The M counter is 13 bits and the A counter 4 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as described in Table 2. The output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop fiIter integrates the current pulses into the varactor line voltage. The charge pump current setting is described in Table 1. A buffered crystal reference frequency suitable for driving further synthesisers is available from pin 9. If not required this output can be disabled by connecting to VCC. The programmable divider output divided by 2, fPD/2 and comparison frequency, fCOMP, can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Table 3.
3
SP5748
Datasheet
j1 j0.5 j2
j0.2 j5
0
0.2
0.5
1
2
5 0*5GHz 1GHz 2j5
2j0.2 2*4GHz
S11: ZO = 50 Normalised to 50
2j0.5 2j1
2j2
Figure 3 - RF input impedance
CLOCK
ENABLE
DATA
225 P1
224 P0
223 T0
222 C1
221 C0
220 R2
219 R1
218 R0
217 RD
216 MSB FREQUENCY DATA
20 LSB
216 to 20 R2, R1, R0 RD P1, P0 C1, C0 T0
Programmable divider ratio control bits Reference divider control bits (see Table 2) Reference divider mode select (see Table 2) Port control bits (see Table 3) Charge pump current bits (see Table 1) Test mode enable bit
Figure 4 - Data format
C1 0 0 1 1
C0 0 1 0 1
Charge pump current (A) 230 1000 115 500
18pF 39pF

2 3
SP5748
Table 1 - Charge pump current
Figure 5 - Crystal oscillator application
4
Datasheet
RD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Division ratio 2 4 8 16 32 64 128 256 3 5 10 20 40 80 160 320 P1 X 0 0 1 1 P0 X 0 1 0 1 T0 0 1 1 1 1
SP5748
Test mode description Normal operation Charge pump sink Charge pump source Charge pump disable Port P1= fCOMP, P0 = fPD/2
Table 3 - Test modes
300 VIN (mVRMS INTO 50)
OPERATING WINDOW 40 30 10
Table 2 - Reference divider control
80 150
1000 2400 FREQUENCY (MHz)
Figure 6 - Typical input sensitivity
1.6GHz 50-900MHz 1650-2400MHz 2 SP5748 3 10 10n VCO 3
39p 18p
38.9MHz
SP5748
Figure 7 - Example of double conversion from VHF/UHF frequencies to TV IF
130V 68p 15n 13.3k
Optional application using on-chip crystal controlled oscillator
18p
39p
22k 16k BCW31 47k 2.2n
112V
1 2
14 13 12
TUNER 1n 1n 15V OSCILLATOR OUTPUT
REFERENCE ENABLE CONTROL MICRO DATA CLOCK P1
3 4 5 6 7
SL 5748
11 10 9 8
P0
Figure 8 - Typical application of SP5748
5
SP5748
Applications
Datasheet
A generic set of Application Notes AN168 for designing with synthesisers such as the SP5748 has been written, covering aspects such as loop filter design and decoupling. This application note is published on the Zarlink Semiconductor web site http:/www.zarlink.com. A generic test/demonstration board has been produced which can be used for the SP5748; the circuit diagram is shown in Figure 9, with component values in Table 4. The board can be used for the following purposes:
q q q q q
There are two ways of achieving a higher phase comparator sampling frequency: (1) Reduce the division ratio between the reference source and the phase comparator (2) use a higher reference source frequency. Approach (2) may be preferred for best performance since it is possible that the noise floor of the reference osciliator may degrade the phase comparator performance if the reference division ratio is very small. Loop bandwidth The majority of applications for which the SP5748 is intended require a loop filter bandwidth of between 2kHz and10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped.
Measuring RF sensitivity performance. Indicating port function. Synthesising the voltage controlled oscillator. Testing of external reference. Measurement of phase noise performance.
Reference source The SP5748 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase comparator noise within the loop bandwidth is: +20log10 LO frequency ( Phase comparator frequency)
Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Value/type 18pF 2*2nF 68pF 1nF 1nF 10nF 100nF 4*7F 100nF 10pF 1nF 100pF 100pF 4*7nF 100pF 4*7F 10nF 39pF 100pF
Component C20 C21 LED 1 LED 2 R1 R4 R6 R7 R8 R9 R10 R11 R12 R13 R14 S1 T1 VCO X1
Value/type 1nF 1nF HLMPK-150 HLMPK-150 4*7k 4*7k 13*3k 22k 1k 0 16 16 16 68 SW DIP-2 BCW31 POS_2000 4MHz
Table 4 - Component values for Figure 9
6
J1 POWER CONNECTOR 15V VCC C7 130V C9 18V RF2 EXT REF C3 R8 R9 T1 R6
2 3 4 5 10 9 8 12 13 1 14 1
C16
2 3
C8
4 5
130V
C2 C1 C6 R7 R10 C14 R11 VCC LK1 R12 C20 R13
J2 VARACTOR
2 1
J5 LK2 X1
11
LK2 is fitted for normal operation C5 C4 SP 5748
C18
RF INPUT 18V RF1 C19
VT
VCO
Figure 9 - SP5748 evaluation board
18V LED1
7
DATA
3
ENABLE R1 R4 P1 S1 J4
1 2 P0 PORT OUTPUTS 6
4
5
VCO tuning range = 1370MHz to 2000MHz C21
RF OUT
CLOCK LED2 C11
6
C15
C13
C12
Datasheet
C17 RF3 COMP OUTPUT
R14
SP5748
7
SP5748
Datasheet
Top view
Bottom view
Figure 10 - SP5748 evaluation board layout
8
Datasheet
VCC
SP5748
VCC
500
500 CHARGE PUMP
RF INPUTS 200 DRIVE
Figure 11a RF inputs
VCC
Figure 11b Loop amplifier
PORT
25k
Figure 11c Enable, Data and Clock inputs
Figure 11d Output ports
VCC
VCC
CRYSTAL CRYSTAL CAP 1*2mA REF
Figure 11e Reference oscillator
Figure 11f Reference output
Figure 11 - Input/output interface circuits
9
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